In designing circuits, there are many different design strategies that may be implemented to obtain a desired result. For example, a design strategy for reducing power consumption of a circuit design may be considered. One way to implement such a strategy is by using multiple supply voltage (MSV) circuits. They save power by using lower supply voltages on non-critical paths and blocks. In MSV circuits, level conversion must be performed at the interface of blocks operating at different power supply voltages (different “levels”).
A type of MSV is called Clustered Voltage Scaling (CVS) in which the supply voltage is lowered selectively on non-critical paths inside a block. In order to implement CVS, level conversion is done at the sequential elements of the circuit (i.e., flip-flops). The clock distribution network can also be implemented at a lower supply voltage (i.e., low-swing clocking) for significant additional power savings. In order to do low-swing clocking in addition to CVS, a double level-converting flip-flop is required: a flip-flop that takes both data and clock inputs at a lower voltage level and that produces data outputs at a higher voltage level.
The conventional implementation for a double level-converting flip-flop may have a regular flip-flop operating at lower supply voltage followed by a regular asynchronous level converter on the Q output. This approach is very slow and power-inefficient. An improvement includes combining the data storage function of a flip-flop with the level conversion function to form a single-level-converting flip-flop. The existing circuit designs introduce contention and are ratioed.
Conventional level converters are ratioed because their operation depends on the precise balancing of the driving strengths and sizes of the transistors in contention. The conventional designs, having contention and being ratioed, means that the ratios of the driving strengths and sizes of the devices in contention must be carefully chosen such that the contention has the desired outcome over all the process corners. Ratioed designs are inherently less robust than non-ratioed designs.